
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:57:30 06/05/2012 
// Design Name: 
// Module Name:    Testbench_LS 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 10ns/1ns

//=============================================================================
module Testbench_LS();

reg clk50m;
initial clk50m=0;
always
begin
  #1;
  clk50m = !clk50m;
end

//=============================================================================
reg nRST = 1'b0;
wire [1:0] USB_FIFOADDR;
wire nUSB_SLOE;
wire nUSB_PKTEND;
wire nUSB_SLWR;
wire nUSB_SLRD;
wire USB_IFCLK;
reg nUSB_FULL;
reg nUSB_EMPTY;
wire nUSB_FD_RDY;
wire [7:0] w_USB_FD_in;
wire [7:0] w_USB_FD_out;
reg [7:0] usb_fd_reg;
assign w_USB_FD_out = nUSB_SLOE ? w_USB_FD_in : 8'bzzzzzzzz;
assign w_USB_FD_in = nUSB_SLOE ? 8'bzzzzzzzz : usb_fd_reg;
assign nUSB_FD_RDY = 0;
wire w_Low_Level;
assign w_Low_Level = 0;
wire [15:0] Logic_IO;

reg [15:0] RAM1_DATA;
reg [15:0] RAM2_DATA;
reg [7:0] Logic_in;
wire w_nRAM1_RD_EN;
wire w_nRAM1_WR_EN;
wire w_nRAM2_RD_EN;
wire w_nRAM2_WR_EN;
wire [17:0] wRAM_ADDR;
wire [15:0] wRAM1_DATA;
wire [15:0] wRAM2_DATA;
wire nRAM_CS;

initial 
begin 
	nUSB_FULL = 1; 
	nUSB_EMPTY = 0;
	RAM1_DATA = 16'H2211;
	RAM2_DATA = 16'H4433;
	Logic_in = 8'h55;
end
Hell_VO Hell_VO_inst (
    .ext_CLK50M(clk50m), 
    .ext_nRST(nRST), 
    .USB_FIFOADDR(USB_FIFOADDR), 
    .nUSB_SLOE(nUSB_SLOE), 
    .nUSB_PKTEND(nUSB_PKTEND), 
    .nUSB_SLWR(nUSB_SLWR), 
    .nUSB_SLRD(nUSB_SLRD), 
    .USB_IFCLK(USB_IFCLK), 
    .nUSB_FULL(nUSB_FULL), 
    .nUSB_EMPTY(nUSB_EMPTY), 
	.nUSB_FD_RDY(nUSB_FD_RDY),
    .USB_FD(w_USB_FD_in),

	.nRAM_CS(nRAM_CS),
	.RAM1_DATA(wRAM1_DATA), 
    .RAM2_DATA(wRAM2_DATA), 
    .RAM_ADDR(wRAM_ADDR), 
    .nRAM1_RD_EN(wRAM1_RD), 
    .nRAM1_WR_EN(wRAM1_WR), 
    .nRAM2_RD_EN(wRAM2_RD), 
    .nRAM2_WR_EN(wRAM2_WR),
	.nLOGICDIR1(),
	.nLOGICDIR2(),

	.Logic_Out(),
	.Logic_In(Logic_in)
    );

IS61LV25616 RAM1_inst (
    .A(wRAM_ADDR), 
    .IO(wRAM1_DATA), 
    .CE_(nRAM_CS), 
    .OE_(w_nRAM1_RD_EN), 
    .WE_(w_nRAM1_WR_EN), 
    .LB_(w_Low_Level), 
    .UB_(w_Low_Level)
    );
IS61LV25616 RAM2_inst (
    .A(wRAM_ADDR), 
    .IO(wRAM2_DATA), 
    .CE_(nRAM_CS), 
    .OE_(w_nRAM2_RD_EN), 
    .WE_(w_nRAM2_WR_EN), 
    .LB_(w_Low_Level), 
    .UB_(w_Low_Level)
    );
//=============================================================================
reg			USB_wr_cmd_req;
reg [39:0]	USB_command;
reg [2:0]	USB_cmd_len;
reg dly_SLRD;
initial
begin
	USB_wr_cmd_req=0;
	USB_command = 0;
	USB_cmd_len = 0;
	dly_SLRD = 1;
end

always @(posedge USB_IFCLK)
begin : temp
	if(USB_wr_cmd_req == 1) begin
		usb_fd_reg = USB_command[39:32];
		nUSB_EMPTY = 1;
		//USB_wr_cmd_req = 0;
		if(!nUSB_SLRD && dly_SLRD && nUSB_SLWR) begin
			USB_cmd_len = USB_cmd_len -1;
			USB_command = {USB_command[31:0],8'b00000000};
			if(USB_cmd_len == 0) begin
				nUSB_EMPTY = 0;
				USB_wr_cmd_req = 0;
			end
		end
		
	end
	dly_SLRD = nUSB_SLRD;
end

task write_short_cmd;
input [7:0] command;
integer i;
begin 
	USB_command = {command,32'h00000000};
	USB_cmd_len = 1;
	USB_wr_cmd_req = 1;
	@(negedge USB_wr_cmd_req);
end
endtask

task write_long_cmd;
input [39:0] command;
integer i;
begin 
	USB_command = command;
	USB_cmd_len = 5;
	USB_wr_cmd_req = 1;
	@(negedge USB_wr_cmd_req);
end
endtask
//=============================================================================
integer i;
initial begin
	#100;
	nRST = 1;
	#100;
	write_short_cmd(8'h00);
	#500;

	write_long_cmd(40'h8000000001);

	#5000;
	$finish;
end

//=============================================================================

endmodule
